This application is based upon and claims the benefit of priority under 35 USC 119 from the prior Japanese Patent Application No. 2001-261160, filed on Aug. 30, 2001, the entire contents of which are incorporated herein by reference.
The present invention relates to an electronic circuit and semiconductor storage device.
Recently, with an increase in the integration degree of semiconductor circuits, attempts have been made to attain improvements in the performance of semiconductor devices, e.g., an improvement in function, a reduction in area, an increase in speed, and a reduction in power consumption. Such advances greatly depend on a reduction in the size of MOS transistors.
In order to reduce the size of a MOS transistor, it is necessary to achieve a reduction in power supply voltage. This is because a reduction in power supply voltage makes it possible to decrease the thickness of the gate oxide film of the MOS transistor and suppress the short channel effect in the MOS transistor. On the other hand, this low-voltage MOS transistor cannot be connected to a high-voltage power supply or signal line.
In addition, a chip includes circuits whose power supply voltages should not be decreased. For example, such circuits are an I/O cell for controlling input/output operation of a single line with respect to the outside of the chip, an analog circuit, and the selection gate of a memory cell in a semiconductor storage device such as a DRAM.
Under the circumstances, a method of applying a plurality of power supply voltages to one chip is employed. In addition, it is recently becoming common practice to attain improvements in characteristics by forming a plurality of types of high- and low-voltage transistors on a single chip and optimizing each transistor.
It is more difficult to attain a reduction in size of a high-voltage transistor than a low-voltage transistor. The effort in design can be reduced by uniformly applying a high power supply voltage to an I/O cell, analog circuits, and the like and using high-voltage transistors, but it must trade off occupied area, operation speed, power consumption, and the like. In order to achieve such an improvement in the performance of a circuit, flexible design is required, e.g., applying a high power supply voltage to only necessary portions and using high-voltage transistors for them while applying a low power supply voltage to a control circuit and high-speed signal path and using low-voltage transistors for them.
One of the problems that arise in such a case is how to match circuit characteristics associated with operation speed and the like between a high-voltage circuit and a low voltage-circuit.
As a method associated with the present invention in a case wherein multiple power supply voltages are used, a method of receiving one power supply voltage from the outside and internally generating the remaining necessary power supply voltages is available. This technique has been used mainly in semiconductor storage devices. A merit of this technique is that the internally generated power supply voltages can be controlled depending on the externally applied power supply voltage. This makes it possible to suppress any circuit characteristic mismatch caused when a plurality of power supply voltages independently vary. According to this technique, however, an internal power supply circuit requires a large area, and hence an increase in integration degree is hindered. Although the technique can suppress independent variations in power supply voltage, it cannot cope with circuit characteristic mismatches caused when the characteristics of a plurality of types of transistors independently vary due to process variations and the like.
The above technique associated with the present invention cannot eliminate the mismatch caused in circuits that independently operate upon receiving a plurality of power supply voltages applied externally or mismatches caused when the characteristics of a plurality of transistors independently vary without hindering an increase in operation speed.
According to one aspect of the invention, there is provided an electronic circuit comprising a first delay compensation circuit which receives a first power supply voltage and a first signal and outputs a first output signal delayed by a first predetermined time, a second delay compensation circuit which receives a second power supply voltage and the first signal and outputs a second output signal delayed by a second predetermined time, a first logic circuit which receives the first power supply voltage and the second output signal output from the second delay compensation circuit and outputs a first operation result by performing first logic operation, and a second logic circuit which receives the second power supply voltage and the first output signal output from the first delay compensation circuit and outputs a second operation result by performing second logic operation.
According to another aspect of the invention, there is provided an electronic circuit comprising a first delay compensation circuit which receives a first power supply voltage, includes a transistor having a first characteristic, receives a first signal, and outputs a first output signal delayed by a first predetermined time, a second delay compensation circuit which receives a second power supply voltage, includes a transistor having a second characteristic, receives a second signal, and outputs a second output signal delayed by a second predetermined time, a first logic circuit which receives the first power supply voltage and the second output signal output from the second delay compensation circuit, performs first logic operation, and outputs a first operation result, and a second logic circuit which receives the first power supply voltage and the first output signal output from the first delay compensation circuit, performs second logic operation, and outputs a second operation result.
According to another aspect of the invention, there is provided an electronic circuit comprising a first level shifter which receives a first signal that has a second voltage at high level, boosts the second voltage to a first voltage, and outputs the first signal, a first delay compensation circuit which receives a first power supply voltage having the first voltage and the first signal output from the first level shifter and outputs a first output signal delayed by a first predetermined time, a second level shifter which receives the first output signal that has the first voltage at high level and output from the first delay compensation circuit, boosts the first voltage to the second voltage, and outputs the first output signal, a second delay compensation circuit which receives the second power supply voltage and the first signal that has the second voltage at high level and outputs a second output signal delayed by a second predetermined time, a third level shifter which receives the second output signal output from the second delay compensation circuit and boosts the second voltage of the second output signal of high level to the first voltage, a first logic circuit which receives the first power supply voltage and the second output signal output from the third level shifter, performs first logic operation, and outputs a first operation result, and a second logic circuit which receives the second power supply voltage having the second voltage and the first output signal output from the second level shifter, performs second logic operation, and outputs a second operation result.
According to another aspect of the invention, there is provided a semiconductor storage device comprising a memory cell array having a plurality of memory cells connected to a plurality of bit lines, column selection gates each provided for a corresponding one of the bit lines to select the bit line, a column decoder which generates a column selection signal for selectively driving the column selection gates, data buffers each of which is provided for a corresponding one of the column selection gates, receives data output from the corresponding column selection gate, and amplifies and outputs the data, a data buffer control logic circuit which generates a data buffer driving signal for selectively driving the data buffers, a first delay compensation circuit which receives a first power supply voltage and a timing signal and outputs a first output signal delayed by a first predetermined time to the data buffer control logic circuit, and a second delay compensation circuit which receives a second power supply voltage and the timing signal and outputs a second output signal delayed by a second predetermined time to the column decoder.
According to another aspect of the invention, there is provided a semiconductor storage device comprising a memory cell array having a plurality of memory cells connected to a plurality of bit lines, column selection gates each provided for a corresponding one of the bit lines to select the bit line, a column decoder which generates a column selection signal for selectively driving the column selection gates, data buffers each of which is provided for a corresponding one of the column selection gates, receives data output from the corresponding column selection gate, and amplifies and outputs the data, a data buffer control logic circuit which generates data buffer drive signals for selectively driving said data buffer, a first level shifter which receives a timing signal that has a second voltage at high level, and outputs the timing signal upon boosting the second voltage to a first voltage, a first delay compensation circuit which receives a first power supply voltage having the first voltage and the timing signal output from the level shifter and outputs a first output signal delayed by a first predetermined time, a second level shifter which receives the first output signal that has the first voltage at high level and output from the first delay compensation circuit, and outputs the first output signal to the data buffer control logic circuit upon boosting the first voltage to the second voltage, a second delay compensation circuit which receives the second power supply voltage and the timing signal that has the second voltage at high level, and outputs a second output signal delayed by a second predetermined time, and a third level shifter which receives the second output signal output from the second delay compensation circuit, boosts the second voltage of the second output signal of high level to the first voltage, and outputs the signal to the column decoder.
According to another aspect of the invention, there is provided a semiconductor storage device comprising a memory cell array having a plurality of memory cells connected to intersections of a plurality of word lines and a plurality of bit lines, a row decoder which generates a word line selection signal for selectively driving the word lines, sense amplifiers each of which is provided for a corresponding one of the bit lines, detects data output from the corresponding bit line, and output the data, a sense amplifier control circuit which generates a sense amplifier driving signal for selectively driving the sense amplifiers, a first level shifter which receives a timing signal that has a second voltage at high level, and outputs the timing signal upon boosting the second voltage to a first voltage, a first delay compensation circuit which receives a first power supply voltage having the first voltage and the timing signal output from the level shifter and outputs a first output signal delayed by a first predetermined time, a second level shifter which receives the first output signal that has the first voltage at high level and output from the first delay compensation circuit, and outputs the first output signal to the data buffer control logic circuit upon boosting the first voltage to the second voltage, a second delay compensation circuit which receives the second power supply voltage and the timing signal that has the second voltage at high level, and outputs a second output signal delayed by a second predetermined time, and a third level shifter which receives the second output signal output from the second delay compensation circuit, boosts the second voltage of the second output signal of high level to the first voltage, and outputs the signal to the column decoder.